Metal bump with an insulating sidewall and method of fabricating thereof

ABSTRACT

Metal bumps for connecting a nonconducting substrate and a chip without lateral shorting are provided. In a first preferred embodiment, an insulating layer covers the entire sidewalls of all the metal bumps. In a second preferred embodiment, predetermined portions of a first metal bump and a second metal bump are covered with an insulating layer. For example, a first predetermined portion of the sidewall of the first metal bump may be zcovered with an insulating layer, while a second predetermined portion of the sidewall of the second sidewall is also covered with an insulating layer.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a metal bump and a method offabricating thereof, and more particularly, to a metal bump with aninsulating sidewall and a method of fabricating thereof.

[0003] 2. Description of the Related Art

[0004] The attachment of a bared die to a glass panel (called COG: chipon glass) is one advanced application for electrically connectingintegrated circuits (ICs) achieving lighter weight, smaller size, lowercost and less power consumption demanded in various display products.Consequently, COG has been successfully adopted for small products (lessthan 4 in.), such as display panels for telephones and copiers, whichhave one or two chips, medium-size products (4-11 in.), such as videocameras and navigation systems, which require 3-12 chips, and largeproducts (more than 11 in.) for notebook PCs.

[0005] The quality and reliability of the liquid crystal display (LCD)module depends on the way in which the driver IC is attached to theglass panel. Anisotropic conductive film (ACF) is the most popularmaterial for attaching the chip to the glass panel. ACF is an adhesivefilm consisting of dispersed, microscopic, electrically conductiveparticles 3-15 μm in diameter and an insulating adhesive film 15-35 μmthick. Various kinds of conductive particles, such as carbon fiber,metal (Ni, solder), and metal (Ni/Au)-coated plastic balls have beenproposed, and the uniformity of the conductive particles distribution isconsidered an influence on the electrical property and reliability ofACF. Also, various types of adhesive materials, such as thermoplastic,thermosetting, and mixed thermoplastic and thermosetting materials havebeen proposed. In general, ACF is classified into two types. One hasconductive particles 5 μm in diameter covered with a very thininsulating layer, wherein the thin insulating layer is broken when theparticles are deformed, the bared conductive particles serving as abridge for electrically connecting the metal bump on the chip and thebonding pad on the glass panel. However, the breaking of the conductiveparticles during the fabricating process cannot be ensured; therefore,there is no guarantee of effective contact between the metal bump andthe bonding pad. The other type of ACF is a double-layer type, whichconsists of one layer filled with conductive particles 3 μm in diameterand the other layer with no conductive particles, so that the functionsof conduction and adhesion are separated. This can ensure the effectivecontact between the metal bump and the bonding pad. Nevertheless, whentoo many conductive particles exist in the space between two adjacentmetal bumps, a lateral connection between the two adjacent metal bumpsis easily formed, resulting in an electrical short.

[0006] Please refer to FIG. 1A to FIG. 1C. FIG. 1A is a top view of thelayout of a glass substrate 10 according to the prior art. FIG. 1B is atop view of the layout of the predetermined area 15 shown in FIG. 1A.FIG. 1C is a top view of the layout of a chip 20 according to the priorart. A glass substrate 10 of the LCD module comprises a first area 12for disposing an array of thin film transistors (TFTs), a second area 14for disposing data IC chips on the predetermined areas 15, and a thirdarea 16 for disposing scan IC chips on the predetermined areas 15. Eachpredetermined area 15 comprises a plurality of first bonding pads 18. Achip 20 which is the data IC chip or the scan IC chip comprises aplurality of second bonding pads 22, wherein each second bonding pad 22corresponds in position to each first bonding pad 18.

[0007] Please refer to FIG. 2A to FIG. 2D. FIG. 2A to FIG. 2D areschematic cross-sectional diagrams of a method of connecting the chip 20and the glass substrate 10 according to the prior art. As shown in FIG.2A, a schematic cross-sectional diagram along the line 2-2 shown in FIG.1B, an ACF 24 is attached to the surface of the glass substrate 10 tocover the first bonding pad 18. As shown in FIG. 2B, a schematiccross-sectional diagram along the line 2′-2′ shown in FIG. 1C, a metalbump 26 is fabricated on the second bonding pad 22 of the chip 20. Asshown in FIG. 2C, the surface of the chip 20 is downwardly placed on thepredetermined area 15 of the glass substrate 10, wherein each metal bump26 corresponds to a first bonding pad 18 of the glass substrate 10. Bymeans of the adhesion of the ACF 24 and the downwardly exerted pressure,the chip 20 is tightly attached to the glass substrate 10. A thermalprocess is then performed to cure the ACF 24. Therefore, the conductiveparticles 25 sandwiched between the top of the metal bump 26 and thesurface of the first bonding pad 18 serve as an electrically connectingbridge. However, as shown in FIG. 2D, the distribution of the conductiveparticles 25 cannot be controlled in processing, and thereby manyconductive particles 25 that exist between adjacent metal bumps 26 maylaterally connect with each other to cause electrical shorts. Especiallywhen the size of the metal bump 26 is incorrectly designed or thealignment between the metal bump 26 and the first bonding pad 18 isinaccurate, the conductive particles 25 are more easily laterallyconnected in the narrow distance between the two adjacent metal bumps26. This will significantly decrease the functioning and reliability ofthe LCD module.

SUMMARY OF THE INVENTION

[0008] The object of the present invention is to provide a metal bumpwith an insulating sidewall and a method of making thereof to preventadjacent metal bumps from being is electrically connected by theconductive particles in the ACF.

[0009] The object of the present invention is to provide a plurality ofmetal bumps for connecting a nonconducting substrate and a chip. Themetal bumps comprise at least a first metal bump having a firstsidewall, the first sidewall comprising a first predetermined area; andat least a second metal bump having a second sidewall, the secondsidewall comprising a second predetermined area adjacent to the firstpredetermined area; wherein at least the first predetermined area iscovered with an insulating layer. In a first preferred embodiment, aninsulating layer covers the entire sidewall of both the first and secondmetal bump. In a second preferred embodiment, predetermined portions ofthe first metal bump and the second metal bump are covered with aninsulating layer. For example, the first predetermined area of the firstsidewall may be covered with an insulating layer, while the secondpredetermined area of the second sidewall is also covered with aninsulating layer. Alternately, the first predetermined area of the firstsidewall may be covered with an insulating layer, while a thirdpredetermined on the second sidewall but outside the secondpredetermined area may be covered with an insulating layer.

[0010] Another object of the present invention is to provide a method offorming a plurality of metal bumps. (a) Provide a chip whose surfacecomprises a plurality of metal pads. (b) Form the plurality of metalbumps on the plurality of metal pads respectively. The plurality ofmetal bumps comprises at least a first metal bump and at least a secondmetal bump. The first metal bump comprises a first sidewall having afirst predetermined area covered with an insulating layer. The firstpredetermined area is adjacent to a second predetermined area on thesidewall of the second metal bump.

[0011] It is an advantage of the present invention that the metal bumpwith insulating sidewall is effective in preventing electrical shortscaused by the conductive particles 35. This can widely improve thefunctioning and reliability of the LCD module.

[0012] This and other objects of the present invention will no doubtbecome obvious to those of ordinary skill in the art after having readthe following detailed description of the preferred embodiment which isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings referred to herein are to be understood as not beingdrawn to scale except where specifically noted, the emphasis insteadbeing placed upon illustration of the principles of advantages of thepresent invention. In the accompanying drawings:

[0014]FIG. 1A is a top view of the layout of a glass substrate accordingto the prior art.

[0015]FIG. 1B is a top view of the layout of the predetermined areashown in FIG. 1A.

[0016]FIG. 1C is a top view of the layout of a chip according to theprior art.

[0017]FIG. 2A to FIG. 2D are schematic cross-sectional diagrams of amethod of connecting the chip and the glass substrate according to theprior art.

[0018]FIG. 3A is a top view of a plurality of metal bumps according thefirst preferred embodiment of the present invention.

[0019]FIG. 3B is a cross-sectional diagram of the metal bump along line3-3 shown in FIG. 3A for connecting a glass substrate and a chip 34.

[0020]FIG. 4A to FIG. 4F are cross-sectional diagrams of a method offorming the metal bump shown in FIG. 3.

[0021]FIG. 5A to FIG. 5F are cross-sectional diagrams of another methodof forming the metal bump shown in FIG. 3.

[0022]FIG. 6A is a top view of the metal bump according to the secondpreferred embodiment of the present invention. FIG. 6B is across-sectional diagram of the metal bump along line 6-6 shown in FIG.6A for connecting the glass substrate and the chip.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] First Embodiment

[0024] Please refer to FIG. 3A and FIG. 3B. FIG. 3A is a top view of aplurality of metal bumps 42 according the first preferred embodiment ofthe present invention. FIG. 3B is a cross-sectional diagram of the metalbump 42 along line 3-3 shown in FIG. 3A for connecting a glass substrate30 and a chip 34. In the first preferred embodiment of the presentinvention, a metal bump 42 is employed to connect a first bonding pad 32on a glass substrate 30 and a second bonding pad 36 on a chip 34. Themetal bump 42 is fabricated on the second bonding pad 36 of the chip 34,and the sidewall of the metal bump 42 is covered with an insulatinglayer 44 for isolating adjacent metal bumps 42. When the chip 34 isdownwardly placed on a predetermined area of the glass substrate 30corresponding to the metal bump 42 at the first bonding pad 32, theadhesion of ACF 38 attached to the glass substrate 30 binds chip 34 onthe glass substrate 30. Accordingly, the conductive particles 39 thatare sandwiched by the top of the metal bump 42 and the surface is of thefirst bonding pad 32 serve as an electrically connecting bridge. Inaddition, since the insulating layer 44 is formed on the sidewall ofeach metal bump 42, the conductive particles that exist between adjacentmetal bumps 42 are isolated to prevent electrical shorts from beingcaused by lateral connection of the conductive particles 35. In areaswhere the second bonding pads 36 are tightly packed, the metal bump 42with insulating sidewalls is effective in preventing electrical shortsfrom the conductive particles 35. This can significantly improve thefunctioning and reliability of the LCD module.

[0025] Please refer to FIG. 4A to FIG. 4F. FIG. 4A to FIG. 4F arecross-sectional diagrams of a method of forming the metal bump 42 shownin FIG. 3. As shown in FIG. 4A, the surface of the chip 34 comprises thebared second bonding pad 36 and a protective layer 40. In thisembodiment, the second bonding pad 36 is made of aluminum, and theprotective layer 40 is made of nitride for protecting the completedintegrated circuits on the chip 34. According to a method of forming themetal bump 42 in the present invention, a photoresist layer 45 isfirstly formed on the chip 34. Then, a photolithography process andetching process are employed to define the pattern of the metal bump 42and remove a predetermined area of the photoresist layer 45 so as toform a cavity 43 that exposes the second bonding pad 36, as shown inFIG. 4B. Next, a metal layer 46 is deposited on the chip 34 to fill thecavity 43, and then the metal layer 45 positioned on the photoresistlayer 45 is removed to level off the surface of the metal layer 45positioned over the cavity 43, as shown in FIG. 4C. After completelyremoving the remaining photoresist layer 45, as shown in FIG. 4D, theremaining metal layer 46 serves as the metal bump 42. Next, theinsulating layer 44 made of silicon oxide or silicon nitride isdeposited on the chip 34 to cover the top and sidewall of the metal bump42, as shown in FIG. 4E. Finally, as shown in FIG. 4F, by using areactive ion etch (RIE) method to perform an anisotropic dry etchingprocess, the insulating layer 44 positioned on the top of the metal bump42 and on the surface of the chip 34 is removed, while the insulatinglayer 44 positioned on the sidewall of the metal bump 42 remains. Thiscompletes the metal bump 42 with insulating sidewalls shown in FIG. 3.

[0026] Please refer to FIG. 5A to FIG. 5F. FIG. 5A to FIG. 5F arecross-sectional diagrams of another method of forming the metal bump 42shown in FIG. 3. According this method of forming the metal bump 42 inthe present invention, a photoresist layer 45 is firstly formed on thechip 34, as shown in FIG. 5A. Then, by using a photolithography processand a first etching process, the pattern of the metal bump 42 is definedand a predetermined area of the photoresist layer 45 is removed so as toform a first cavity 48, as shown in FIG. 5B. The first cavity 48 exposesthe second bonding pad 36 and part of the protective layer 40 thatsurrounds the second bonding pad 36. Next, as shown in FIG. 5C, theinsulating layer 44 is deposited on the chip 34 to fill the first cavity48. Next, a second etching process is performed to remove the insulatinglayer 44 positioned over the surface of the photoresist layer 45, thesecond bonding pad 36 and the protective layer 40, and remain theinsulating layer 44 positioned on the sidewall of the first cavity 48 soas to form a second cavity 50, as shown in FIG. 5D. Next, the metallayer 46 is deposited on the chip 34 to fill the second cavity 50, andthen the metal layer 46 positioned on the photoresist layer 45 isremoved to is level off the surface of the metal layer 46 positioned inthe second cavity 50, as shown in FIG. 5E. Finally, as shown in FIG. 5F,after removing the photoresist layer 45, the metal layer 46 with theinsulating layer 44 positioned on the sidewall is employed as the metalbump 42 as shown in FIG. 3.

[0027] Second Embodiment

[0028] Insulating layer 44 can achieve the purpose of isolating adjacentmetal bumps 42 by covering only specific areas of the sidewalls of themetal bumps 42. Please refer to FIG. 6A and FIG. 6B. FIG. 6A is a topview of the metal bump 42 according to the second preferred embodimentof the present invention. FIG. 6B is a cross-sectional diagram of themetal bump 42 along line 6-6 shown in FIG. 6A for connecting the glasssubstrate 30 and the chip 34. According to the second preferredembodiment, the chip 34 has a plurality of metal bumps 42 comprising atleast a first metal bump 421 and at least a second metal bump 422,wherein a first predetermined area 521 on the sidewall of the firstmetal bump 421 is adjacent to a second predetermined area 522 on thesidewall of the second metal bump 422. In order to isolate the firstpredetermined area 521 and the second predetermined area 522, a firstinsulating layer 441 is formed to cover the first predetermined area 521on the sidewall of the first metal bump 421. No insulating layer isneeded for covering the second predetermined area. With regard to otherareas on the sidewall of the second metal bump 422, a second insulatinglayer 442 can be selectively formed on a specific area depending on theisolation effect in demand. The first insulating layer 441 isolates theconductive particles 39 that exist between the first predetermined area521 and the second predetermined area 522, preventing electrical shortscaused by the lateral connection of the conductive particles 39. Thisimproves the functioning and reliability of the LCD products.

[0029] Those skilled in the art will readily observe that numerousmodifications and alterations of the device may be made while retainingthe teaching of the invention. It is understood, for example, that onlythe two adjacent areas of the sidewalls of adjacent metal bumps could becovered with an insulating layer. Accordingly, the above disclosureshould be construed as limited only by the metes and bounds of theappended claims.

What is claimed is:
 1. A plurality of metal bumps for connecting anonconducting substrate and a chip, comprising: at least a first metalbump having a first sidewall, the first sidewall comprising a firstpredetermined area; and at least a second metal bump having a secondsidewall, the second sidewall comprising a second predetermined areaadjacent to the first predetermined area; wherein at least the firstpredetermined area is covered with an insulating layer.
 2. The pluralityof metal bumps of claim 1, wherein the second predetermined area iscovered with an insulating layer.
 3. The plurality of metal bumps ofclaim 1, wherein the second sidewall further comprises a thirdpredetermined area outside the second predetermined area, and the thirdpredetermined area is covered with an insulating layer.
 4. The pluralityof metal bumps of claim 1, wherein the first sidewall is completelycovered with an insulating layer.
 5. The plurality of metal bumps ofclaim 1, wherein the first sidewall and the second sidewall are bothcompletely covered with an insulating layer.
 6. The plurality of metalbumps of claim 1, wherein the nonconducting substrate comprises aplurality of first metal pads, and the chip comprises a plurality ofsecond metal pads which correspond to the first metal pads.
 7. Theplurality of metal bumps of claim 6, wherein each metal bump is fixedbetween the first metal pad and the correspondent second metal pad. 8.The plurality of metal bumps of claim 1, wherein the space between twoadjacent metal bumps that are sandwiched by the nonconducting substrateand the chip is filled with an anisotrpic conductive film (ACF).
 9. Theplurality of metal bumps of claim 1, wherein the insulating layer ismade of silicon oxide or silicon nitride.
 10. The plurality of metalbumps of claim 1, wherein the nonconducting substrate is a glasssubstrate.
 11. A method of forming a plurality of metal bumps,comprising: (a) providing a chip whose surface comprises a plurality ofmetal pads; (b) forming a photoresist layer on the chip; (c) performingan etching process to remove the photoresist layer covering the metalpad so as to form a hole that exposes the metal pad; (d) filling thehole with a metal layer; (e) completely removing the remainingphotoresist layer; (f) depositing an insulating layer on the chip tocover the metal layer; and (g) performing an anisotropic dry etchingprocess to remove the insulating layer positioned on the top of themetal layer and on the surface of the chip so as to leave the insulatinglayer positioned on the sidewall of the metal layer.
 12. The method ofclaim 11, wherein the metal layer is made of Au.
 13. The method of claim11, wherein the insulating layer is made of silicon oxide or siliconnitride.
 14. The method of claim 11, wherein the anisotropic dry etchingprocess is a reactive ion etching (RIE) method.
 15. The method of claim11, wherein the metal bump is used for connecting the chip with anonconducting substrate, and the space between two adjacent metal bumpsis filled with an anisotropic conductive film (ACF).
 16. A method offorming a plurality of metal bumps, comprising: (a) providing a chipwhose surface comprises a plurality of metal pads; (b) forming aphotoresist layer on the chip; (c) performing a first etching process toremoving the photoresist layer that covers the surface and periphery ofthe metal pad so as to form a first hole that exposes the metal pad; (d)depositing an insulating layer on the chip to fill the first hole; (e)performing a second etching process to remove the insulating layerpositioned on the surface of the metal pad and remain the insulatinglayer positioned on the sidewall of the first hole, and thereby a secondhole is formed; (f) filling the second hole with a metal layer; and (g)removing the remaining photoresist layer.
 17. The method of claim 16,wherein the metal layer is made of Au.
 18. The method of claim 16,wherein the insulating layer is made of silicon oxide or siliconnitride.
 19. The method of claim 16, wherein the metal bump is used forconnecting the chip with a nonconducting substrate and the space betweentwo adjacent metal bumps is filled with an anisotropic conductive film(ACF).